Abstract
Most current training methods for Artificial Neural Networks (ANNs) run as software emulations, as opposed to an on-chip training approach. Although it is convenient to have training done through software as opposed to on a hardware build, there are several drawbacks to this approach. The primary cost of this convenience is the amount of time it takes to train an ANN. Emulated training methods are slower than real-time on-chip training, with the amount of training time increasing with the complexity of the ANN. When training in real-time each neuron can be trained at once, taking advantage of the inherent parallelism of ANNs, and decreasing training times markedly. This thesis includes a discussion of an analog hardware implementation for training neural networks, and an evaluation and design explanation of an ANN which has been built on physical hardware as a proof-of-concept. The ANN is designed to perform pattern recognition on handwritten digits from zero to nine, and uses the Modified National Institute of Standards and Technology data set as a source for the figures used in training. The “output-layer” section of this ANN, where all of the training is completed, is built entirely in analog hardware in order to prove the potential advantages over training in software.