Abstract
As the complexity of Neural Networks increases, off-chip training computation becomes expensive, and training time increases significantly as the dataset size grows. The advantage of on-chip analog training is the ability to use parallelism by training multiple neurons simultaneously and convergence speed is limited only by the speed of the analog electronics used in the system. A three-layer Artificial Neural Networks (ANN) architecture was implemented for recognizing handwritten number patterns from the Modified National Institute of Standards and Technology (MNIST) database. The system utilizes analog feedback circuits, implemented on a breadboard, to continuously adjust the Output Layer Neuron (OLN) weights during training mode, establishing real-time on-chip training. This work expands beyond the previous twoneuron ANN system by increasing the number of OLNs to evaluate the scalability and parallelism of on-chip analog training. Successful on-chip training was validated through convergence of the training weights while each neuron correctly recognized its assigned number and ignored the remaining digits. The results show that the system maintains consistent training behavior as the network size increases, highlighting the potential of scalable analog on-chip training for neural networks.