Abstract
This chapter presents a review of cascaded H-bridge multilevel inverter (CHMLI) for nanoscale CMOS implementation using the phase disposition pulse width modulation (PD-PWM) technique, in particular. Traditional two-level inverters are limited often by significant harmonic distortion and substantial voltage stress on electronic components. These limitations can be effectively addressed using multilevel inverters, which offer improved performance through a smooth output sine wave. The proposed CHMLI enhances the output voltage quality and reduces total harmonic distortion (THD). Specifically the chapter delves into the construction and comparison of nine-level and 11-level inverters for nanoscale CMOS implementation. Using an exhaustive simulation and experimentation it can be shown that the phase disposition method allows the switching of H-bridges to achieve finer voltage steps and improved performance. The results also indicate that the novel CHMLI configuration in nano-CMOS offers superior alternative for high-power applications that demand high efficiency and reliability. The chapter provides a comprehensive comparison between the nine-level and 11-level inverters, demonstrating the scalability and effectiveness of the proposed multilevel inverter design in the nanoscale.